The present invention relates to a semiconductor integrated circuit having a power supply voltage detecting function, and more particularly, a semiconductor integrated circuit, whose circuit functions are all ceased at a power supply voltage of a value or lower, while in part at a power supply voltage of a higher value, but whose circuit functions are all operable at a power supply voltage of a sufficiently further higher value, whereby a wrong operation in a state of a low voltage is prevented from occurring.
In a non-volatile semiconductor memory in which data write and electrical erase can be performed (flash memory EEPROM), its internal operations are controlled in such a manner that a power supply voltage V.sub.DD is detected, and during a time when a value of the V.sub.DD is equal to or lower than a first voltage level (V.sub.POWERON), all the functions of its internal circuits are ceased, while during a time when a value of the V.sub.DD is higher than the first voltage level (V.sub.POWERON) but still lower than a second voltage level (V.sub.LVDD), which is lower than an operation guarantee voltage, a write/erase operation cannot be performed, though a data read operation can be performed. Thereby, wrong write and wrong erase both prevented from occurring.
That is, a flash EEPROM works as a read-only memory when a power supply voltage V.sub.DD is higher than a V.sub.POWERON level but lower than a V.sub.LVDD level, and data in a memory cell is not changed by a write/erase operation therein.
Since an operation is unstable when a power supply voltage V.sub.DD is higher than the V.sub.POWERON level, but it is lower than the V.sub.LVDD level which is a regular operation guarantee voltage level, data write and erase, which entail a change in data in a memory cell, are not performed. This is achieved in such a manner that a level of the power supply voltage V.sub.VDD is internally detected and a write/erase command from the outside is not accepted, if V.sub.DD &lt;V.sub.LVDD. A write/erase operation is ceased when a state of V.sub.DD &gt;V.sub.LVDD is given by some influence or other, even after a write/erase operation is started by receiving an external command in a state of V.sub.DD &lt;V.sub.LVDD l.
In order to perform the above mentioned control, there are a need for a circuit detecting two voltage levels of the V.sub.POWERON and the V.sub.LVDD in a chip.
Since the V.sub.POWERON level is a voltage level which guarantees a read operation, it is linked with an internal power supply margin. Generally, in the case of a CMOS circuit, the level has more chances to be set at a voltage of the order of the sum of threshold voltages of a p-channel MOS transistor and an n-channel MOS transistor.
FIG. 1A shows a conventional voltage detection circuit for detecting the V.sub.POWERON level. The V.sub.POWERON in the voltage detection circuit is given by V.sub.POWERON =V.sub.THN +.vertline.V.sub.THP.vertline. (V.sub.THN and V.sub.THP are respectively threshold voltages of n and p-channel MOS transistors). In this circuit, a resistor R.sub.31 and a current path between the source and drain of an n-channel MOS transistor (hereinafter referred to as NMOS) 41 are connected in series between nodes of a power supply voltage V.sub.VDD and the ground potential. The gate of the NMOS 41 is connected to a connection node between an end of the current path and the resistor R.sub.31. Besides, a current path between the source and drain of an p-channel MOS transistor (hereinafter referred to as PMOS) 42 and a resistor R32 are in series connected between the nodes of the power supply voltage V.sub.VDD and the ground potential. The gate of the PMOS 42 is connected to the connection node between the resistor R31 an end of the current path of the NMOS 41.
An amplifier circuit 43 is connected to a connection node between an end a current path of the PMOS 42 and the resistor R.sub.32 , wherein the amplifier circuit 43 comprises two inverters having cascade connection and produces a detection signal S.sub.POWERON showing that a power supply voltage V.sub.DD is lower or higher than a V.sub.POWERON through voltage amplification of a signal at the connection node.
In such a constitution, a detection signal S.sub.POWERON is H level when a power supply voltage V.sub.DD is lower than a V.sub.POWERON level (V.sub.THN +.vertline.V.sub.THP.vertline.) and a detection signal level is L level when a power supply voltage V.sub.DD is higher than the V.sub.POWERON level (V.sub.THN +.vertline.V.sub.THP.vertline.).
FIG. 1B shows another circuit constitution of a conventional voltage detection circuit for detecting a V.sub.POWERON level in a similar manner. This circuit employs a pn junction diode 44 instead of the NMOS 41 of FIG. 1A and is further different from it in that the V.sub.POWERON level is given by V.sub.f +.vertline.V.sub.THP.vertline.(V.sub.f is a voltage drop in a forward direction of a PN junction diode).
Another voltage detection level V.sub.LVDD of a power supply has more chances to be determined by a power supply circuit in a write or erase operation as a factor.
FIG. 2A shows a symbolic diagram of a non-volatile transistor with a floating gate and control gate, which is used as a flash EEPROM memory cell and FIG. 2B is a table collectively showing voltages supplied to the control gate (VG), drain (VD), source (VS) and back gate (VSUB) in data read/write/erase operations of the non-volatile transistor. As shown in the figure, an operation voltage of the memory cell requires to be higher voltage, positive or negative, (10V, 6V, -7V) for a write/erase operation as compared with a read operation.
In a flash EPROM, these high voltages are internally generated, for example, by use of a booster circuit as shown in FIG. 3. The booster circuit comprises diodes 51 connected in series, and capacitors 52 and inverters 53, 54 used for boosting an anode and cathode of each diode 51 alternately with clock signals of different phases.
A value of a boosted voltage V.sub.out obtained in the booster circuit is strongly dependent on the number of the diodes (N) and a value of a power supply voltage V.sub.DD and given by the following equation: EQU V.sub.out.ltoreq.N.times.(V.sub.DD -Vf)
where Vf is a voltage drop in a diode.
Therefore, the number of necessary steps (N) in a booster circuit is different according to an operation voltage for guarantee.
A relation in magnitude between V.sub.POWERON and V.sub.LVDD levels in a integrated circuit of V.sub.DD =5V has a large difference and for example, the settings are like V.sub.POWERON =2V and V.sub.LVDD =3.5V.
FIG. 4 shows an example of a conventional voltage detection circuit for detecting the V.sub.LVDD level. Two resistors 61, 62 are in series connected between a node of the power supply voltage V.sub.DD and the node of the ground voltage. The power supply voltage V.sub.DD is divided by the two resistors 61, 62 and supplied to a non-inversion input terminal (+) of an operational amplifier 63. A reference potential V.sub.ref is supplied to an inversion input terminal (-) of the operational amplifier 63 and the operational amplifier 63 compares both input potentials in magnitude. A comparison output of the operational amplifier 63 is amplified by an inverter 64 and thereby a detection signal SLV.sub.DD of H level or L level is generated.
The above mentioned reference voltage V.sub.ref is a voltage which has no dependence on the V.sub.DD level and, for example, as shown FIG. 5, it is generated in a circuit constituted of diodes 71, 72, resistors 73 to 75 and an operational amplifier 76. The circuit is a generally known BGR (Band Gap Reference) circuit.
Now, when values of the resistors 61, 62 are respectively indicated by Ra and Rb, the detection signal S.sub.LVDD output from the voltage detection circuit of FIG. 4 achieves H level if the following equation is satisfied, which is: EQU VDD&lt;{(Ra+Rb)/Rb}V.sub.ref
In the case where an integrated circuit is guaranteed so that it is operable with a power supply voltage of 5V, since such a condition V.sub.LVDD &gt;&gt;V.sub.POWERON can be set, it has not been considered that a relation in magnitude between V.sub.LVDD and V.sub.POWERON levels is reversed, even when there are fluctuations in respective levels of V.sub.LVDD and V.sub.POWERON However,
However, in a progress toward a lower voltage in an integrated circuit, there has been encountered a case where a relation in magnitude between V.sub.LVDD and V.sub.POWERON levels is reversed in an integrated circuit in which a guarantee of V.sub.DD =2.7V is required or a further lower power supply voltage has to be used for operation guarantee. For example, a combination of the power supply detection circuit for a V.sub.POWERON level of FIG. 1A and the power supply detection circuit for a V.sub.LVDD level will be considered.
In FIG. 1A, a value of V.sub.POWERON (V.sub.THN +.vertline.V.sub.THP.vertline.) generally has a central value of 1.8V at room temperature. In the following, it will be analyzed in what range of voltage the value is fluctuated according to an operational temperature or a process dispersion. For example, it is assumed that a dispersion of a threshold value is .+-.0.1V, threshold vs. temperature characteristics are +0.1V at -40.degree. C., 0V at room temperature and -0.1V at +100.degree. C. The minimum value at a higher temperature for which a process dispersion of a V.sub.POWERON level is considered, which was 1.8V, is 1.4V, and the maximum value at a lower temperature, for which a process dispersion is considered, is 2.2V. That is, a V.sub.POWERON level is spread in the range of 1.4V to 2.2V with 1.8V as a central value.
On the other hand, a V.sub.LVDD which is a detection level in the voltage detection circuit of FIG. 4 is determined by the following equation: EQU VLVDD={(R1-R2)/R2}V.sub.ref
The V.sub.ref in the equation is the reference voltage generated in a BGR circuit shown in FIG. 5, and a value thereof is almost not dependent of a power supply voltage or an operational temperature and constantly assumes 1.25V. Therefore, a V.sub.LVDD level is not affected by a dispersion of a threshold voltage of a transistor and it is set as a constant voltage without any temperature characteristics.
In the progress toward a lower voltage as described above, wherein an operation is guaranteed at a condition V.sub.DD =2.7V, a V.sub.LVDD level should be set at a lower value than that and it is required by common sense that the V.sub.LVDD is set on the order of 2.2V, which is on the order of 80% of V.sub.DD (2.7.times.0.8).
In this case, in the worst condition of a lower temperature, a V.sub.LVDD level has a chance to be lower than a V.sub.POWERON level. Besides, an original intention cannot be achieved that the worst guarantee voltage for a write/erase operation is set at a higher value than the lowest guarantee voltage for a read operation.
While in the above description, a non-volatile semiconductor memory (flash EEPROM) is taken up as an example of a semiconductor integrated circuit, whose circuit functions are all ceased at a power supply voltage of a value or lower, while in part at a power supply voltage of a higher value, but whose circuit functions are all operable at a power supply voltage of a sufficiently further higher value, the above mentioned problem also occurs in a semiconductor circuit whose function is controlled by detecting a power supply voltage at two voltage levels.